Referring to FIGS. 1A and 1B, there is illustrated a prior art method for forming an isolation layer of a semiconductor device based on a general LOCOS process. As shown in FIG. 1A, a thin oxide layer 11 is positioned between a substrate 10 (formed, for example, of silicon) and a nitride layer 13 (which serves as an oxidation mask) in order to relieve stress due to a difference in thermal properties between the substrate 10 and the nitride layer 13.
Subsequently, a LOCOS process (as shown in FIG. 1B) is applied to the substrate, so as to form a field oxide layer 19 on the semiconductor device. However, when forming the field oxide layer 19 with the LOCOS technique, the field oxide layer 19 grows not only vertically, but also laterally and this growth intrudes somewhat underneath the edges of the nitride layer 13, so that the active region becomes reduced. In addition, the field ions implanted below the field oxide layer 19 diffuse into the active region, which aggravates the reduction of the active region. This lateral encroachment on the active region by the field oxide layer 19 under the nitride layer 13, known as "bird's beak", can grow to a thickness of about half the thickness of the field oxide layer 19.
With the standard LOCOS process, the field oxide layer thickness has to be reduced in order to reduce the length of the bird's beak encroaching upon the active region; otherwise, the operative active region will be inadequate. The reduction in field oxide thickness, however, causes an increase in the capacitance between the substrate and an interconnection line on chip, thus degrading the characteristics of an IC. In other words, the speed of transferring signals decreases. In addition, the threshold voltage (V.sub.T) of the parasitic field transistor is dropped. Accordingly, leakage current under the field oxide layer increases rapidly with reduction in field oxide thickness, resulting in poor isolation between adjacent active regions. Consequently, reducing the thickness of the field oxide layer 19 in order to decrease the length of the bird's beak is limited by the need for isolation.
In the last few years, research and development efforts in LOCOS isolation technologies have been directed to reducing the amount of oxide encroachment in the standard LOCOs process by constraining the growth of the bird's beak without reducing the thickness of the field oxide layer 19.
To reduce the bird's beak, a method has been proposed in which a nitride layer is formed on and beside a pad oxide layer in order to seal the pad oxide layer, and then a field oxidation is carried out with the nitride layer serving as an oxidation mask. Another method, known as "polysilicon buffered LOCOS", has been proposed in article entitled "High Reliability and High Performance 0.35 .mu.m Gate-Inverted TFT's for 16 Mbit and SRAM Applications Using Self-Aligned LDD Structures", International Electron Devices Meeting 1992 at p. 100 (published in 1988). This method is illustrated in FIG. 2. As shown in this figure, a polysilicon buffer layer 23 is additionally formed between a nitride layer 13 which serves as an oxidation mask, and a pad oxide layer 25 of SiO.sub.2 in order to suppress the bird's beak growth attributed to the lateral oxidation of pad oxide layer 25 interior of the nitride layer 13. With the polysilicon buffered LOCOS, a field oxide layer 19 is formed with the bird's beak suppressed relative to the case of FIG. 1B.
However, the top of the field oxide layer 19 excessively protrudes from the surface of substrate 10. As a result, there arises difficulty in forming a pattern with an appropriate degree of resolution on a photoresist when processes for gate line formation, wiring formation and so on, as well as the subsequent processes of LOCOS, are performed. In addition, since the field oxide layer 19 is not formed deep within the substrate 10, the punch-through and isolation characteristics become inferior because of the shortness of the channel length of the parasitic field transistor.
In addition to the above techniques, several other isolation techniques have been suggested. For example, there is a SILO (sealed interface local oxidation) process and a SWAMI (side wall masked isolation) process. These modifications of the LOCOS process, however, have many a problem to be solved. With regard to the SWAMI process, the problem of bird's beak, (that is, the encroachment of the field oxide layer on the active region) is not generated. However, it too has problems. Most of these are due to the limitation that the silicon substrate cannot be consistently etched at the preferred slope angle in either wet etch or dry etch. In the case of wet etch, depending on the crystallinity of the substrate, the silicon substrate can be etched only at certain angles with an alkaline aqueous solution, such as KOH or NaOE. Thus, there is no way to control the slope. For example, a wafer is etched at an angle of 45.degree. in the &lt;110&gt; direction. In addition, a further problem arises in that K.sup.+ or Na.sup.+ ions contaminate the silicon substrate.
On the other hand, when a dry etch process is applied to the silicon substrate uniform control of the slope is always a problem.
One of the most troublesome problems in the standard LOCOS process is that, although the width and length of the active region is reduced so as to be useful for a highly integrated device, the thickness of the field oxide layer is not reduced. Thus, the new device has the same heat cycle as the old device. Another problem is that channel stop dopants must be implanted into the field region at a high density in order to stabilize the punch-through voltage in the isolation region of a short channel. Thus, the actual width of the active region is limited to that of the prior processes because the implanted channel stop dopants laterally diffuse into the active region.
Consequently, as the degree of integration in a semiconductor device becomes high, the width of the active field is remarkably reduced. For example, the active region in a 64 Mbit DRAM device is only about 0.4 .mu.m wide in the conventional LOCOS process. Further, the amount of lateral encroachment of channel stop dopants on the active region .DELTA.W is considerable, causing a great loss to the width of the active region.
As shown in FIG. 3, if the active region is designed to be L in length and 0.4 .mu.m in width, W, and if .DELTA.W is 0.1 82 m, the actual width of the active region is 0.2 .mu.m (0.4-2.times..DELTA.W). This is because the channel stop dopants diffuse from both sides of active region to double the encroachment on the active region.
In fact, in case of the standard LOCOS process, it is believed that the formation of a field oxide layer of about 5,000 Angstroms thickness permits .DELTA.W to be about 0.15 to 0.20 .mu.m.
As would be expected, the reduction in width of the active region limits the amount of current between the source and drain of a transistor, thus raising the threshold voltage of transistor. As a result, the performance of a transistor made by the standard LOCOS is inferior.
Without particular difficulties, the LOCOS process has been used to make a semiconductor device with a maximum line width of about 1.0 .mu.m (1 Mbit DRAM scale), but it begins to have great difficulty in developing a semiconductor device with a maximum line width of about 0.8 .mu.m (4 Mbit DRAM scale).
Since 1985, many efforts have been made to overcome the LOCOS process limitations. One effort is being directed to developing a modified LOCOS technique. Another approach to device isolation is a trench isolation process. In this process, a silicon substrate is etched to form a trench which is subsequently filled with an insulating material.
Because of its technical difficulty, the trench isolation process has, thus far, rarely been applied to actual mass production. In contrast, the modified LOCOS isolation technique has played an important role in developing a semiconductor device of the 64 Mbit DRAM scale (having a maximum line width of 0.4 m) and is highly apt to be applied to mass production.
Another combination technology process has been suggested for an isolation process which can provide planar surfaces by the use of only a single photolithographic masking step, with no encroachment on active region. In this combination technology process, when active regions are apart from each other a relatively great distance (i.e. a wide trench), they are separated from each other by using the LOCOS isolation process. On the other hand, when active regions are apart from each other a relatively short distance (i.e. a narrow trench), a BOX isolation process is applied in order to separate the active regions. This combination technology process is reported in U.S. Pat. No. 4,892,614.
Referring to FIGS. 4A through 4H there is stepwise illustrated a method for isolating the active regions of a semiconductor device which employs a combination of the LOCOS and BOX isolation techniques.
As shown in FIG. 4A, on a substrate 10, there is grown a first thermal oxide layer 12 upon which a nitride layer 13 is deposited using a low pressure chemical vapor deposition (hereinafter referred to as "LPCVD") process.
After deposition of the nitride layer 13, a photoresist layer 16 is coated on the nitride layer 13 and patterned, so as to define the placement of active regions. The nitride layer 13 and the first thermal oxide layer 12 are etched according to the photoresist pattern.
Subsequently, the substrate 10 is etched, so as to form a plurality of trenches 20a-20d. Trenches 20a and 20b are relatively narrow. That is to say, an active region at one side of the narrow trench is relatively near to another active region at the other side of the trench. In contrast, trenches 20c and 20d are relatively wide. In other words, two active regions 18 at the opposite sides of the wide trench 20c are a relatively great distance away from each other. In this figure, reference numeral 21 designate corners of the trenches.
Secondly, FIG. 4B shows the semiconductor device after a second thermal oxide layer 22 has been grown on the areas of the substrate 10 which were exposed by forming the trenches. Prior to this, all the photoresist pattern 16 left on the active regions 18 was removed. Compared with the semiconductor device of FIG. 4A, the second thermal oxide layer 22 serves to slightly round off the corners 21 (FIG. 4B) of the trenches in order to relieve the amount of stress at the corners 21.
Thereafter, as shown in FIG. 4C, a second nitride layer 24 is deposited, followed by the deposition of an oxide layer 26 using a chemical vapor deposition (CVD) process. At this time, the thickness of the oxide layer 26 is chosen to be thick enough to fill the narrow trenches 20a and 20b, while not filling the wide trenches 20c and 20d. As a result, small depressions 27a are formed over the narrow trenches 20a and 20b where the oxide layer 26 fills the trenches. In contrast, in the wide trenches 20c and 20d where the oxide layer 26 on opposite sidewalls does not meet, deep depressions 27b are formed and left unfilled.
FIG. 4D shows a cross-section of the semiconductor device after an anisotropic etch has been carried out. In the wide trenches 20c and 20d, all the oxide layer 26, the second nitride layer 24 and the second thermal oxide layer 22 are removed from under the deep depressions 27b by the etch, thereby exposing the silicon substrate through gaps surrounded by sidewall oxide layer 29 (i.e., the remains of layer 26). On the other hand, in narrow trenches 20a and 20b, the second nitride layer 24 is not removed, since the sidewall oxide layer 29 fills up the trenches and thus protects them from the etch.
FIG. 4E illustrates the formation of a field oxide layer 19 while carrying out a field oxidation process. After the remaining sidewall oxide layer 29 is removed, a field oxide layer 19 is formed in the wide trenches 20c,20d but not in the narrow trenches 20a and 20b since the substrate 10 there remains covered with second nitride layer 24. In contrast, the field oxide layer 19 is grown on the exposed substrate 10 of the wide trenches 20c and 20d. As seen in FIG. 4E, in the wide trench thermal field oxide layer 19 grows underneath the edge of the second nitride layer 24, resulting in bird's beak 31. This bird's beak does not grow up to the top edge of the active regions 18, so that there is no reduction in the active regions 18.
Next, the nitride layers 13 and 24 are removed by dipping them in hot phosphoric acid and an oxide layer 32 is deposited by a chemical vapor deposition (CVD) process so thickly as to fill up all the trenches 20a-20d, as illustrated in FIG. 4F. The thickness of the oxide layer 32 is made sufficient to form a near-planar surface at its top surface.
FIG. 4G shows a cross-section of the semiconductor device after the oxide layer 32 has been subjected to etch-back.
Finally, as shown in FIG. 4H, a gas oxide layer 34 is grown over the exposed surfaces of the substrate.
As stated above, the narrow trenches 20a are filled with oxide layer 32, resulting in a BOX process structure. In contrast, the wide trenches 20c and 20d are partially filled with the field oxide layer 19 over which the oxide layer 32 is deposited in the wide trenches, resulting in a combination BOX/LOCOS process structure. In other words, where the active regions are near each other, they are separated by a narrow trench isolation region which is formed using the BOX process while, where the active regions are relatively far from each other, they are separated using a combination of the BOX and the LOCOS processes.
Apparently, this method for making isolation region structures of semiconductor devices with a combination of LOCOS and BOX techniques not only satisfies all requisites for high integration of a semiconductor device (such requisites being a planar surface with no bird's beak and so on) but also is much simpler in that only a single photolithographic masking step is required.
However, the above-stated isolation method is somewhat cumbersome because, when the trenches 20a-20d are filled with the oxide layer, complicated steps must be carried out. More specifically, the conventional combination method comprises: (1) oxidizing a substrate to form a thermal oxide layer in trenches; (2) CVD depositing oxide in the trenches and applying etch back to the oxide to form sidewalls in the trenches; (3) carrying out a field oxidation process to form a field oxide layer in a wide trench; and (4) depositing another CVD oxide layer and etching back this, so as to fill up both narrow trenches with the CVD oxide layer and to fill the wide trenches with the CVD oxide and field oxide. The conventional isolation method, therefore, is not able to achieve isolation regions with a homogeneous structure, and results in higher production costs due to its many steps.